Intel’s new programmable chips next year to replace aging products

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Intel has shared its latest programmable chip roadmap, and does not want to sink into the hole by following AMD’s strategy in this area.

“We thankfully don’t fit their strategy,” said Shannon Poulin, corporate vice president of the data center and artificial intelligence group at Intel, in response to a question from HPCwire during a press briefing.

The updated roadmap brings together Intel’s strategy for FPGAs, or field-programmable gate arrays, in line with its manufacturing advancements.

FPGAs can be programmed to perform a range of functions such as AI chips and network acceleration. Companies also use FPGAs to test chip designs or prototype applications.

Intel has been on hold on FPGAs, releasing the last major Agilex chip in 2021, which was fabricated on the 10nm SuperFin process.

The next major Agilex product – which is more of a manufacturing upgrade – will be released in 2023-2024. The M-series FPGA will be on an upgraded 10nm process, which Intel calls “Intel 7”.

The follow-up, the next-generation Agilex chip based on a new architecture, will also arrive in 2023-2024 on Intel 7.

Poulin, who took over the FPGA division last year, acknowledged that the company hasn’t kept pace to meet vendor needs. Intel had no availability or portfolio of FPGAs for the low-end market on a modern manufacturing process, Poulin said.

“I really felt we had to look at the supply chain. We had a lot of our products – we still have a lot of our products – on legacy supply nodes, a lot of those nodes are not made at Intel, and I’m talking about knots that are, you know, 5-10-20 years old, in some cases,” Poulin said.

Manufacturing consultancy Jabil, which integrates chips into projects for industrial clients, said he expected FPGA shortages go until 2023.

There’s a huge demand for FPGAs in modern equipment in 5G and robotics where cutting-edge FPGAs, fabricated on modern processes, are becoming really important, Poulin said.

“We are shifting our entire portfolio to Intel manufacturing,” he said.

Intel is making a series of advancements in its manufacturing processes, including the use of “chiplet” technology which can pack a range of chips into a single chip. Intel is designing an FPGA for this, which brings PCIe 5.0 and the CXL interconnect, and can be paired with a range of chips, such as AI accelerators, GPUs or x86 and RISC-V processors in a single integrated chip. Intel has sampled this product and will put them into production soon, Poulin said.

Intel’s Advanced Interface Bus (AIB) is a die-to-die PHY-level standard that enables a modular approach to system design with an intellectual property (IP) block library of chips. The figure shows an example of a possible heterogeneous system-in-package (SiP) that combines sensors, proprietary ASIC, FPGA, processor, memory, and I/O using AIB as the chip interface. Credit: Intel.

The company works with partners like Texas Instruments, which primarily manufactures analog chips, to connect the FPGA to third-party chiplets. This is done through an interface that Intel calls AIB (Advanced Interface Bus).

“We’re moving to a more chip architecture and a more modular capability, which really opens up a number of opportunities not just for PSG…but also for the company as a whole,” Poulin said.

Agilex D-Series is also on the roadmap, which is aimed at the mid-range market. The chip will have 100,000 logic elements, low-power DDR5 memory, and a new type of “smart fabric” that will improve performance. Initial chips will be sampled in 2023, with volume shipments starting in 2024. The FPGA is targeted for industrial, communications, robotics and other markets.

The next Agilex chip named Sundance Mesa will be about half the size of the D-series chip with about 50,000 logic elements. It will be for artificial intelligence and consumer-oriented applications. Intel has not assigned a series name to this chip.

Intel has been making chips with its Stratix and Agilex FPGAs for four years, but will evolve them to support new interfaces like UCIe, which is emerging as the interconnect for linking various cores into a single chip package.

Intel relies to some extent on chiplets and related interfaces like UCIe and CXL, to advance its FPGA strategy. This is heavily dependent on the company’s manufacturing strategy, which is not progressing as planned with delays in shipments of chips such as the Xeon processors codenamed Sapphire Rapids and the Gaudi 2 AI chip.

Meanwhile, AMD continued the rapid integration of Xilinx, which it acquired earlier this year after a lengthy review period. AMD wasted no time in releasing a cohesive roadmap that included CPUs, GPUs, software-defined FPGAs, and fixed-function ASICs.

AMD executives tour chip conferences to talk about the FPGA and ASIC roadmap. FPGAs can perform on-chip functions using software, but AMD combines fixed-function logic, like ASICs, with programmable logic adapters like FPGAs where customizations like expansions can be layered custom headers, or add or remove new accelerator functions on programmable logic.

Intel is looking to catch up, but Poulin said the company wants to finalize its strategy, even if it takes time. The modular approach — which will be made possible by interfaces like UCIe and CXL — will allow Intel to create a more flexible chip design, Poulin said.

“I think it’s fair…that we keep adding to our portfolio, but we’re not going to strategically follow them down this rabbit hole of hardened IP that people don’t want or most people don’t. don’t want,” Poulin said. .

Poulin said there were two choices where you could choose to harden the IP – on the fabric itself or on a chip, which Intel has with the AIB interface.

“One of the things you don’t want to do, which is one of the things [AMD’s] Versal has done, is hardened a bunch of stuff that a subset of people will use and won’t have a modular way of making exactly the right product that someone wants, because then you end up costing (in terms infrastructure), leaks (in terms of current), and with a product that is over-engineered for an individual market,” Poulin said.

Intel’s strategy plays out well in the infrastructure processing unit (IPU) space, where the company has beefed up the IP on the fabric.

“We’re going to have a modular approach so we can put exactly hard IP on exactly the customers who want it,” Poulin said.

Intel Process Node Roadmap and Milestones for 2022. Presented by Pat Gelsinger at the Intel Investor Meeting February 17, 2022.

But Intel has its challenges ahead, which depend in part on whether the company sticks to its manufacturing roadmap. Intel CEO Pat Gelsinger has laid out an aggressive roadmap in 2021 to advance four nodes in five years, which is much faster than the typical two-year advance in chipmaking. Another big question for Intel remains whether the company will be able to customize these chips, which the company mainly does for top customers with large custom chip orders.

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