New Electronics – Cadence Design Flows Achieve Certification for TSMC’s N4P and N3E Processes

Cadence Design Systems announced that TSMC has certified its digital and custom/analog design workflows for the latest TSMC N4P and N3E processes in support of the new Design Rules Handbook (DRM) and FINFLEX technology.

The companies also provided the corresponding N4P and N3E Process Design Kits (PDKs) to accelerate design innovation for advanced nodes, AI and large-scale computing.

Cadence said customers have already started using the latest TSMC process technologies and certified Cadence flows.

Cadence and TSMC R&D teams worked closely together to ensure the digital stream met TSMC’s advanced N4P and N3E certification requirements.

Cadence’s complete RTL to GDS stream includes Innovus Implementation System, Quantus Extraction Solution, Quantus FS Solution, Tempus Timing Signoff Solution and ECO Option, Pegasus Verification System, Characterization Solution Liberate, the Voltus IC Power Integrity Solution and Voltus-Fi Custom Power Integrity The Solution.

Cadence Genus synthesis solution and iSpatial predictive technology are also enabled for TSMC N4P and N3E process technologies.

The digital full stream offers several key features that will support TSMC N4P and N3E process technologies. This includes native optimization of mixed-height cell rows from synthesis to engineering change order (ECO) approval for optimal PPA; placement based on standard cell lines; implementation results that correlate well with approval for faster design closure; enhanced via pillar support for better design performance; large libraries containing many multi-height, threshold voltage (VT), and driving force cells; characterization and analysis of temporal robustness cells; reliability modeling using STA taking aging into account; and enhancements to the CCSP model providing improved accuracy and simplified characterization for analysis through the Voltus IC Power Integrity solution.

Cadence Virtuoso design platform, which includes Virtuoso schematic editor, Virtuoso ADE product suite and Virtuoso layout suite and Specter simulation platform, which includes Specter X Simulator, Specter Accelerated Parallel Simulator (APS), Specter eXtensive Partitioning Simulator (XPS) and the Specter RF Option, have been certified for TSMC N4P and N3E processes.

The Virtuoso design platform provides tight integration with the Innovus implementation system, which augments the methodology for implementing mixed-signal designs through a common database.

The Custom Design Reference Flow (CDRF) has also been enhanced to support the latest N4P and N3E process technologies. The Virtuoso schematic editor, Virtuoso ADE suite, and built-in Specter X simulator help customers efficiently handle corner simulations, statistical analysis, design centering, and circuit optimization.

The Virtuoso Layout Suite has been tuned for efficient layout layout, leveraging a line-based layout methodology with placement, routing, padding and layout functionality. dummy insert; improved analog migration and layout reuse functionality; built-in parasite extraction and EM-IR controls; and built-in physical verification capabilities.

“By continuing to work closely with Cadence, we’re ensuring customers can use our most advanced N4P and N3E technologies and Cadence-certified digital and custom/analog streams with confidence,” said Dan Kochpatcharin, Head of Design Infrastructure Management division at TSMC. “This joint effort combining TSMC’s technological advancements with Cadence’s cutting-edge design solutions helps our joint customers meet stringent power and performance requirements and bring their next-generation silicon innovations to market quickly. “

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