MOUNTAIN VIEW, CALIFORNIA., May 26, 2021 / PRNewswire / –
Highlights of this announcement:
- Synopsys Design Solutions Certified for Latest Version of TSMC’s 3nm Process Technology DRM and SPICE Models
- Synopsys and TSMC have collaborated on enabling Advanced Design using the Fusion Design Platform and Synopsys Custom Design Platform so that mutual customers can make the most of the PPA benefits of advanced process technologies from TSMC.
- Benefits of benchmark methodology already validated in mutual customer designs, increased number of successful registrations
Synopsys, Inc. (Nasdaq: SNPS) announced today that TSMC has certified Synopsys digital and custom design solutions based on TSMC’s latest Design Rules Manual (DRM) and Process Design Kits for its advanced 3 nanometer (nm) process technology. This certification is the result of an extended collaboration over several years to provide co-optimized tools, flows and methodologies that allow customers to reach the maximum right of the process in terms of power, performance and area (PPA), accelerating the next generation of high performance innovation. computer chip designs (HPC), mobile, 5G and AI. To learn more about Synopsys certified solutions, the many test chips already performed on these nodes, how to deploy Synopsys design platforms and more, visit the Synopsys booth at the TSMC 2021 Online Technical Symposium to June 1-2.
“TSMC’s cutting edge technology required new levels of EDA collaboration and innovation to achieve the high performance and low power goals of 3nm processing technology,” said Suk lee, vice president of TSMC’s Design Infrastructure Management division. “Our long-term collaboration with Synopsys has helped accelerate access to TSMC’s latest process offering and maximize its benefits. We will continue to work closely together to enable next generation designs for HPC, mobile, 5G and AI applications. . “
Synopsys’ highly integrated fusion design platform is a critical part of this successful collaboration of advanced nodes, providing full and full-flow design convergence and close approval correlation for TSMC’s 3nm technology. Synopsis’ Merge compiler™ and the IC compiler™ ll place-and-route product, achieve optimized synchronization quality of results (QoR) through new global and retail-route technological innovations. Advances in full-flow total power optimization and simultaneous legalization and optimization technology help achieve required total power profiles and overall optimized PPA design metrics.
Other implementation technologies deployed as part of the 3nm collaboration include support for advanced routing with colouration and abutment consideration and innovative toggle optimization that facilitates performance-driven, low-power designs. . In addition, the design compiler® The NXT synthesis product, a key component of the Fusion design platform, has been enhanced to provide a more converged design flow through closer time correlation with IC Compiler II, benefiting all designs targeting the N3 process. .
Synopsys 3nm Collaboration with TSMC Also Includes PrimeTime® supports low voltage variation and supports TSMC placement rules to enable converged ECO shutdown during implementation and approval. Synopsys PrimePower supports 3nm physical rules for power approval including leakage and dynamic power with StarRC™ improvements in extraction modeling to provide the necessary precision.
Additional approval solutions certified for TSMC 3nm technology include NanoTime Custom Timing Approval, ESP Custom Equivalency Verification, and QuickCap® NX stray field solver solution. Synopsys IC Validator ™ physical approval has been improved to support all advanced process requirements, including new dummy fill features for improved density, layout dependent effects for layout verification against schematic and improved delta voltage rule debugging efficiency for the DRC.
The custom compiler™ The design and layout solution, which is part of the Synopsys custom design platform, provides enhanced productivity for designers using TSMC’s advanced process technologies. Many improvements to the custom compiler, validated by early 3nm users, including the Synopsys DesignWare IP team, reduce efforts to meet the requirements of 3nm technology. The PrimeSim Synopsys™ HSPICE®, PrimeSim™ SPICES, PrimeSim™ Pro and PrimeSim™ XA simulators, as part of PrimeSim™ Continuum Solution, provides improved turnaround time for TSMC 3nm designs and provides approval coverage for circuit simulation and reliability requirements.
“The ecosystem and our customers benefit from the close collaborations of TSMC and Synopsys to push achievable limits and accelerate access to each new technological process,” said Shankar Krishnamoorthy, Managing Director and Corporate Staff for the Group of digital design at Synopsys. “Our latest digital and personalized R&D collaborations for 3nm technology have provided new levels of technological innovation to overcome process challenges and thus open a new chapter of opportunities for our mutual customers to deliver their product roadmaps. advanced in a timely manner. “
Synopsys technology files are available from TSMC for the 3nm process technology. For a complete list of TSMC-certified Synopsys digital and custom platform solutions, please visit: www.synopsys.com/tsmc.
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner of innovative companies developing the electronic products and software applications on which we rely every day. As a S&P 500 company, Synopsys has long been a global leader in electronic design automation (EDA) and semiconductor intellectual property and offers the broadest portfolio of testing tools and services. sector application security. Whether you are a system-on-a-chip (SoC) designer creating advanced semiconductors or a software developer writing more secure, high-quality code, Synopsys has the solutions to deliver innovative products. Learn more at www.synopsys.com.
SOURCE Synopsys, Inc.